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may 2007 hyb18t512400b[c/f] hyb18t512800b[c/f] HYB18T512160B[c/f] 512-mbit double-data-rate-two sdram ddr2 sdram rohs compliant products internet data sheet rev. 1.1
we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com internet data sheet hyb18t512[40/80/16]0b[c/f] 512-mbit double-data-rate-two sdram qag_techdoc_rev400 / 3.2 qag / 2006-07-21 2 03292006-ybym-wg0z hyb18t512400b[c/f], HYB18T512160B [c/f], hyb18t512800b[c/f] revision history: 2007-05, rev. 1.1 page subjects (major chan ges since last revision) all adapted internet edition all added more product types previous revision: 2007-01, rev. 1.05 all qimonda template update previous revision: 2006-02, rev. 1.04 internet data sheet rev. 1.1, 2007-05 3 03292006-ybym-wg0z hyb18t512[40/80/16]0b[c/f] 512-mbit double-data-rate-two sdram 1overview this chapter gives an overview of the 512-mbit double- data-rate-two sdram product family and describes its main characteristics. 1.1 features the 512-mbit double-data-rate-two sdra m offers the following key features: ? 1.8 v 0.1 v power supply 1.8 v 0.1 v (sstl_18) compatible i/o ? dram organizations with 4 and 8 data in/outputs ? double-data-rate-two architecture: two data transfers per clock cycle four internal ban ks for concurrent operation ? programmable cas latency: 3, 4, 5 and 6 ? programmable burst length: 4 and 8 ? differential clock inputs (ck and ck ) ? bi-directional, differentia l data strobes (dqs and dqs ) are transmitted / received with da ta. edge aligned with read data and center-aligned with write data. ? dll aligns dq and dqs transitions with clock ?dqs can be disabled for single-ended data strobe operation ? commands entered on each positive clock edge, data and data mask are referenced to both edges of dqs ? data masks (dm) for write data ? posted cas by programmable additive latency for better command and data bus efficiency ? off-chip-driver impedance adjustment (ocd) and on- die-termination (odt) for better signal quality ? auto-precharge operation for read and write bursts ? auto-refresh, self-refresh and power saving power- down modes ? average refresh period 7.8 s at a t case lower than 85 c, 3.9 s between 85 c and 95 c ? programmable self refres h rate via emrs2 setting ? programmable partial array refresh via emrs2 settings ? dcc enabling via emrs2 setting ? full and reduced strengt h data-output drivers ? 1kb page size for 4 & 8, 2kb page size for 16 ? package: p(g)-tfbga-6 0 and p(g)-tfbga-84 ? rohs compliant products 1) ? all speed grades faster than ddr2?400 comply with ddr2?400 timing specifications when run at a clock rate of 200 mhz. table 1 performance table for ?25f and ?2.5 1) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. product type speed code ?25f ?2.5 unit speed grade ddr2?800d 5?5?5 ddr2?800e 6?6?6 ? max. clock frequency @cl6 f ck6 400 400 mhz @cl5 f ck5 400 333 mhz @cl4 f ck4 266 266 mhz @cl3 f ck3 200 200 mhz min. ras-cas-delay t rcd 12.5 15 ns min. row precharge time t rp 12.5 15 ns min. row active time t ras 45 45 ns min. row cycle time t rc 57.5 60 ns internet data sheet rev. 1.1, 2007-05 4 03292006-ybym-wg0z hyb18t512[40/80/16]0b[c/f] 512-mbit double-data-rate-two sdram table 2 performance table for ?3(s) table 3 performance table for ?3.7(f) table 4 performance table for ?5 product type speed code ?3 ?3s unit speed grade ddr2?667c 4?4?4 ddr2?667d 5?5?5 ? max. clock frequency @cl5 f ck5 333 333 mhz @cl4 f ck4 333 266 mhz @cl3 f ck3 200 200 mhz min. ras-cas-delay t rcd 12 15 ns min. row precharge time t rp 12 15 ns min. row active time t ras 45 45 ns min. row cycle time t rc 57 60 ns product type speed code ?37f ?3.7 unit speed grade ddr2?533b 3?3?3 ddr2?533c 4?4?4 ? max. clock frequency @cl5 f ck5 266 266 mhz @cl4 f ck4 266 266 mhz @cl3 f ck3 266 200 mhz min. ras-cas-delay t rcd 11.25 15 ns min. row precharge time t rp 11.25 15 ns min. row active time t ras 45 45 ns min. row cycle time t rc 56.25 60 ns product type speed code ?5 units speed grade ddr2?400b 3?3?3 ? max. clock frequency @cl5 f ck5 200 mhz @cl4 f ck4 200 mhz @cl3 f ck3 200 mhz min. ras-cas-delay t rcd 15 ns min. row precharge time t rp 15 ns min. row active time t ras 40 ns min. row cycle time t rc 55 ns internet data sheet rev. 1.1, 2007-05 5 03292006-ybym-wg0z hyb18t512[40/80/16]0b[c/f] 512-mbit double-data-rate-two sdram 1.2 description the 512-mb ddr2 dram is a high-speed double-data- rate-two cmos dram device containing 536,870,912 bits and is internally configured as an quad-bank dram. the 512-mb device is organized as either 32 mbit 4i/o 4 banks, 16 mbit 8i/o 4banks or 8mbit 16 i/o 4 banks chip. these devices achieve high speed transfer rates starting at 400 mb/sec/pin for general applications. see table 1 for performance figures. the device is designed to comply with all ddr2 dram key features: 1. posted cas with additive latency 2. write latency = read latency - 1 3. normal and weak strength data-output driver 4. off-chip driver (ocd) impedance adjustment 5. on-die termination (odt) function all of the control and address inputs are synchronized with a pair of externally supplied diff erential clocks. inputs are latched at the cross point of di fferential clocks (ck rising and ck falling). all i/os are synchronized with a single ended dqs or differential dqs-dqs pair in a source synchronous fashion. a 16-bit address bus for 4 and 8 organized components and a 15-bit address bus for 16 components is used to convey row, column and bank address information in a ras - cas multiplexing style. the ddr2 device operates with a 1.8 v 0.1 v power supply. an auto-refresh and self-refresh mode is provided along with various power-saving power-down modes. the functionality described and the timing specifications included in this data sheet are for the dll enabled mode of operation. the ddr2 sdram is available in fbga package. internet data sheet rev. 1.1, 2007-05 6 03292006-ybym-wg0z hyb18t512[40/80/16]0b[c/f] 512-mbit double-data-rate-two sdram table 5 ordering information for lead-free products (rohs compliant) product type org. speed cas-rcd-rp latencies 1)2)3) 1) cas: column address strobe 2) rcd: row column delay 3) rp: row precharge clock (mhz) package note hyb18t512400bf-2.5 4 ddr2-800e 6-6-6 400 pg-tfbga- 60 4) 4) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. hyb18t512800bf-2.5 8 ddr2-800e 6-6-6 400 pg-tfbga- 60 HYB18T512160Bf-2.5 16 ddr2-800e 6-6-6 400 pg-tfbga- 84 hyb18t512400bf-25f 4 ddr2- 800d 5-5-5 400 pg-tfbga- 60 hyb18t512800bf-25f 8 ddr2- 800d 5-5-5 400 pg-tfbga- 60 HYB18T512160Bf-25f 16 ddr2- 800d 5-5-5 400 pg-tfbga- 84 hyb18t512400bf-3s 4 ddr2- 667d 5-5-5 333 pg-tfbga- 60 hyb18t512800bf-3s 8 ddr2- 667d 5-5-5 333 pg-tfbga- 60 HYB18T512160Bf-3s 16 ddr2- 667d 5-5-5 333 pg-tfbga- 84 hyb18t512400bf-3 4 ddr2- 667c 4-4-4 333 pg-tfbga- 60 hyb18t512800bf-3 8 ddr2- 667c 4-4-4 333 pg-tfbga- 60 HYB18T512160Bf-3 16 ddr2- 667c 4-4-4 333 pg-tfbga- 84 hyb18t512400bf-3.7 4 ddr2- 533c 4-4-4 266 pg-tfbga- 60 hyb18t512800bf-3.7 8 ddr2- 533c 4-4-4 266 pg-tfbga- 60 HYB18T512160Bf-3.7 16 ddr2- 533c 4-4-4 266 pg-tfbga- 84 hyb18t512400bf-5 4 ddr2-400b 3-3-3 200 pg-tfbga- 60 hyb18t512800bf-5 8 ddr2-400b 3-3-3 200 pg-tfbga- 60 HYB18T512160Bf-5 16 ddr2-400b 3-3-3 200 pg-tfbga- 84 internet data sheet rev. 1.1, 2007-05 7 03292006-ybym-wg0z hyb18t512[40/80/16]0b[c/f] 512-mbit double-data-rate-two sdram table 6 ordering information for lead-containing products note: for product nomenclature see chapter 9 of this data sheet product type org. speed cas-rcd-rp latencies 1)2)3) 1) cas: column address strobe 2) rcd: row column delay 3) rp: row precharge clock (mhz) package hyb18t512800bc-3s 8 ddr2-667d 5-5-5 333 p-tfbga-60 HYB18T512160Bc-3s 16 ddr2-667d 5-5-5 333 p-tfbga-84 hyb18t512800bc-3.7 8 ddr2-533c 4-4-4 266 p-tfbga-60 HYB18T512160Bc-3.7 16 ddr2-533c 4-4-4 266 p-tfbga-84 internet data sheet rev. 1.1, 2007-05 8 03292006-ybym-wg0z hyb18t512[40/80/16]0b[c/f] 512-mbit double-data-rate-two sdram 2 chip configuration this chapter contains the chip configuration and addressing. 2.1 chip configuration the chip configuration of a ddr2 sdram is listed by function in table 7 . the abbreviations used in the ball# and buffer type columns are explained in table 8 and table 9 respectively. the ball numbering for the fbga package is depicted in figure 1 for 4, figure 2 for 8 and figure 3 for 16 . table 7 chip configuration of ddr2 sdram ball# name ball type buffer type function clock signals 4/ 8 organization e8 ck i sstl clock signal ck, complementary clock signal ck f8 ck i sstl f2 cke i sstl clock enable clock signals 16 organization j8 ck i sstl clock signal ck, complementary clock signal ck note: see functional description in x4/x8 organization k8 ck i sstl k2 cke i sstl clock enable note: see functional description in x4/x8 organization control signals 4/ 8 organizations f7 ras i sstl row address strobe (ras), column address strobe (cas), write enable (we) g7 cas i sstl f3 we i sstl g8 cs i sstl chip select control signals 16 organization k7 ras i sstl row address strobe (ras), column address strobe (cas), write enable (we) l7 cas i sstl k3 we i sstl l8 cs i sstl chip select address signals 4/ 8 organizations g2 ba0 i sstl bank address bus 1:0 g3 ba1 i sstl internet data sheet rev. 1.1, 2007-05 9 03292006-ybym-wg0z hyb18t512[40/80/16]0b[c/f] 512-mbit double-data-rate-two sdram h8 a0 i sstl address signal 12:0, address signal 10/autoprecharge h3 a1 i sstl h7 a2 i sstl j2 a3 i sstl j8 a4 i sstl j3 a5 i sstl j7 a6 i sstl k2 a7 i sstl k8 a8 i sstl k3 a9 i sstl h2 a10 i sstl ap i sstl k7 a11 i sstl l2 a12 i sstl l8 a13 i sstl address signal 13 note: x4/x8 512 mbit components nc ? ? note: and x16 512 mbit components address signals 16 organization l2 ba0 i sstl bank address bus 1:0 l3 ba1 i sstl l1 nc ? ? m8 a0 i sstl address signal 12:0, address signal 10/autoprecharge m3 a1 i sstl m7 a2 i sstl n2 a3 i sstl n8 a4 i sstl n3 a5 i sstl n7 a6 i sstl p2 a7 i sstl p8 a8 i sstl p3 a9 i sstl m2 a10 i sstl ap i sstl p7 a11 i sstl r2 a12 i sstl data signals 4/ 8 organization c8 dq0 i/o sstl data signal 3:0 c2 dq1 i/o sstl d7 dq2 i/o sstl d3 dq3 i/o sstl ball# name ball type buffer type function internet data sheet rev. 1.1, 2007-05 10 03292006-ybym-wg0z hyb18t512[40/80/16]0b[c/f] 512-mbit double-data-rate-two sdram d1 dq4 i/o sstl data signal 7:4 d9 dq5 i/o sstl b1 dq6 i/o sstl b9 dq7 i/o sstl data signals 16 organization g8 dq0 i/o sstl data signal 15:0 g2 dq1 i/o sstl h7 dq2 i/o sstl h3 dq3 i/o sstl h1 dq4 i/o sstl h9 dq5 i/o sstl f1 dq6 i/o sstl f9 dq7 i/o sstl c8 dq8 i/o sstl c2 dq9 i/o sstl d7 dq10 i/o sstl d3 dq11 i/o sstl d1 dq12 i/o sstl d9 dq13 i/o sstl b1 dq14 i/o sstl b9 dq15 i/o sstl data strobe 4/ 8 organizations b7 dqs i/o sstl data strobe a8 dqs i/o sstl data strobe 8 organisation b3 rdqs o sstl read data strobe a2 rdqs o sstl data strobe 16 organization b7 udqs i/o sstl data strobe upper byte a8 udqs i/o sstl f7 ldqs i/o sstl data strobe lower byte e8 ldqs i/o sstl data mask 4/ 8 organizations b3 dm i sstl data mask data mask 16 organization b3 udm i sstl data mask upper/lower byte f3 ldm i sstl power supplies 4 8 16 organization a9, c1, c3, c7, c9 v ddq pwr ? i/o driver power supply ball# name ball type buffer type function internet data sheet rev. 1.1, 2007-05 11 03292006-ybym-wg0z hyb18t512[40/80/16]0b[c/f] 512-mbit double-data-rate-two sdram a1 v dd pwr ? power supply a7, b2, b8, d2, d8 v ssq pwr ? i/o driver power supply a3, e3 v ss pwr ? power supply power supplies 4/ 8 organizations e2 v ref ai ? i/o reference voltage e1 v ddl pwr ? power supply e9, h9, l1 v dd pwr ? power supply e7 v ssdl pwr ? power supply j1, k9 v ss pwr ? power supply power supplies 16 organization j2 v ref ai ? i/o reference voltage e9, g1, g3, g7, g9 v ddq pwr ? i/o driver power supply j1 v ddl pwr ? power supply e1, j9, m9, r1 v dd pwr ? power supply e7, f2, f8, h2, h8 v ssq pwr ? i/o driver power supply j7 v ssdl pwr ? power supply a3, e3, j3, n1, p9 v ss pwr ? power supply not connected 4/ 8 organization g1, l3,l7, l8 nc nc ? not connected not connected 4 organization a2, b1, b9, d1, d9 nc nc ? not connected not connected 16 organization a2, e2, l1, r3, r7, r8 nc nc ? not connected other balls 4/ 8 organizations f9 odt i sstl on-die termination control other balls 16 organization k9 odt i sstl on-die termination control ball# name ball type buffer type function internet data sheet rev. 1.1, 2007-05 12 03292006-ybym-wg0z hyb18t512[40/80/16]0b[c/f] 512-mbit double-data-rate-two sdram table 8 abbreviations for ball type table 9 abbreviations for buffer type abbreviation description i standard input-only ball. digital levels. o output. digital levels. i/o i/o is a bidirectio nal input/output signal. ai input. analog levels. pwr power gnd ground nc not connected abbreviation description sstl serial stub terminated logic (sstl_18) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding ball has 2 oper ational states, active low and tristate, and allows multiple devices to share as a wire-or. internet data sheet rev. 1.1, 2007-05 13 03292006-ybym-wg0z hyb18t512[40/80/16]0b[c/f] 512-mbit double-data-rate-two sdram figure 1 chip configuration for 4 components, pg-tfbga-60 (top view) notes 1. v ddl and v ssdl are power and ground for the dll. v ddl is connected to v dd on the device. v dd , v ddq , v ssdl , v ss , and v ssq are isolated on the device. 2. ball position l8 is a13 for 512-mbit and is not connected on 256-mbit 0 3 3 7 & |